Memory systems include memory interfaces that enable data to be read and written from a memory array. Conventional memory systems store binary data in individual memory cells of a memory array, reading and writing data bits (i.e., binary “0”s and “1”s) to memory cells using driving voltages (e.g., read voltage, write voltage, driving voltage, and the like). Interfaces enable other devices to access and use data stored in memory cells.
FIG. 1 illustrates a conventional memory system. Conventional memory system 100 includes memory bank 102. To access individual memory cells within memory bank 102, column logic 104 and row logic 106 are directed by control logic 108 when accessing a particular memory cell. Data stored in memory system 100 is accessed by other devices using a parallel interface.
Conventional interfaces convert data from parallel to serial formats for transmission and then back to a parallel format upon receipt, which incurs significant time delays and reduces capacity. In some cases, conventional interfaces perform multiple conversions, which require large chip layouts and design during fabrication, including large numbers of pins or packaging (interfacing circuitry with other devices or systems). Conventional parallel interfaces are used with various memory architectures, including static random access memory (SRAM) and dynamic random access memory (DRAM). Conventional interfaces with SRAM architectures typically have control lines that cause various functions to be performed when active. Control lines, along with address lines and data lines, contribute to large chip architectures. A chip select control line is used to select an address within a memory device and also allows for multiple chips to be tied together in a memory system. A read select control line is used to read data from a memory device. In contrast, a write select control line is used to write data to a memory device. When a chip select control line is combined with a read select control line, data is read from a memory cell and driven to the output of the memory device. When chip select and write select control lines are active, data is written to a memory cell indicated by address lines that refer to a particular row and column address for the memory device.
Data lines may either be dedicated input and output lines, such as those shown in FIG. 2, or combined into a single set of data lines, as in the example shown in FIG. 3. Conventional SRAM interfaces require large numbers of pins in order to support large memory capacities, which results in large, expensive packages. As packaging sizes increases, inductance and capacitance also increase, reducing access speeds. Conventional DRAM interfaces also have performance limitations.
FIG. 4 illustrates a conventional DRAM interface 400, which multiplexes data to share input/output ports to reduce the number of connections (i.e., pins). For example, conventional DRAM interfaces multiplex address and payload data to share input/output ports. In some examples, payload data may refer to data included in the body (i.e., not in the header or trailing bits of data) of a packet, segment, frame, or other type of data encapsulation. However, this is time consuming, increases power consumption, and increases access times and decreases throughput. Further, DRAM memory devices transfer large amounts of data, requiring large numbers of pins and packaging.
FIG. 5 illustrates a conventional memory system using a DRAM interface. Conventional memory system 500 includes a disk controller 502 which interfaces with memory devices 504. Memory devices 504 can be implemented as a single or multiple memory devices. As part of the disk controller 502, processor 506, DRAM controller 508, physical (PHY)/link (media access control or MAC) layer logic block 510, error checking and correction (ECC) 512, and disk port interface 514 for ports P0-P3 are included. Data is read and written by disk controller 502 over DRAM controller 508 to memory devices 504. However, conventional system 500 is inefficient in that the single link between DRAM controller 508 and memory devices 504 often becomes a performance bottleneck, limiting the amount of memory system 500 throughput.
Ports P0-P3 bid for access to data in memory devices 504 simultaneously. Disk controller 502 may receive several bids to read or write data from memory devices 504. To handle the bids, disk controller 502 uses DRAM controller 508 to prioritize bids from external devices and perform handshakes to establish a path to memory devices 504. Bids transiting disk controller 502 create bottlenecks in the data flow. To alleviate the bottleneck, a very complex memory controller design is typically required. Design complexity results in substantial costs due to increased gate count. Further, high signaling speeds and large numbers of registers in complex memory system design also increase power consumption.
Continuing efforts are being made to improve memory interfaces.
It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGS. are not necessarily to scale. Although various examples of the invention are disclosed in the accompanying drawings, the invention is not limited to those specific examples.